1. Field
Exemplary implementations of the present invention relate to an analog-to-digital conversion circuit, an analog-to-digital conversion method, and an image sensor, which can decrease a non-linear error of a digital signal when performing analog-to-digital conversion.
2. Description of the Related Art
Recently, the demand for digital cameras has explosively increased with the development of visual communication using the Internet. Moreover, as mobile communication terminals mounted with a camera, such as a PDA (personal digital assistant), an IMT-2000 (International Mobile Telecommunications-2000) terminal and a CDMA (code division multiple access) terminal, are popularized, the demand for small-sized camera modules has increased.
A camera module includes an image sensor. In general, an image sensor refers to a device that converts an optical image into an electrical signal. Examples of common image sensors include a CCD (charge coupled device) or a CMOS (complementary metal oxide semiconductor) image sensor.
The CCD has a complicated driving scheme and high power consumption. Furthermore, since the number of mask processes required for fabrication is relatively large, fabrication processing is complex. In addition, since a signal processing circuit cannot be realized in a chip, it is difficult to realize the CCD in one chip.
However, in the CMOS image sensor, monolithic integration of control, driving, and signal processing circuits in a single chip is possible. Accordingly, attention has recently been paid to the CMOS image sensor. Also, when compared to a CCD image sensor, the CMOS image sensor has a lower cost due to a low voltage operation, low power consumption, compatibility with peripheral devices, and the recued complexity a standard CMOS fabrication process.
The CMOS image sensor includes a plurality of unit pixels. The pixels output analog signals (hereinafter, referred to as “pixel signals”) with voltage levels corresponding to light incident thereon. The CMOS image sensor generates pixel data by analog-to-digital converting these pixel signals, and the pixel data are used in storing and outputting an image. The CMOS image sensor includes an analog-to-digital conversion circuit which is used to convert an analog signal into a digital signal, for analog-to-digital conversion of a pixel signal.
In general, as a resolution increases, the power consumption and an analog-to-digital conversion time of an analog-to-digital conversion circuit increase. Meanwhile, shot noise increases as the intensity of light incident on a pixel increases. Due to this fact, as the intensity of light increases, the magnitude of quantization noise permitted in the analog-to-digital conversion circuit increases. Accordingly, in a case where the intensity of light incident on a pixel is large, data corresponding to the incident light may be generated with no problem even though a resolution of analog-to-digital conversion is relatively low, when compared to a case where the intensity of light is small. Accordingly, an analog-to-digital conversion circuit that analog-to-digital converts a pixel signal by applying different resolutions based on the intensity of light obtained by determining an approximate intensity of light incident on a pixel (the level of a pixel signal). In the case of using such an analog-to-digital conversion circuit, power consumption and an analog-to-digital conversion time may be decreased.
FIG. 1 is a configuration diagram of a related analog-to-digital conversion circuit in which different resolutions are applied according to the level of an input voltage.
Referring to FIG. 1, an analog-to-digital conversion circuit includes a comparator 110, a resolution control unit 120, and an analog-to-digital conversion unit 130.
The comparator 110 is configured to compare an input voltage VIN to a reference voltage VREF, and output a comparison result. For example, the comparator 110 may output a logic high level in the case where the input voltage VIN is larger than the reference voltage VREF, and may output a logic low level in the case where the input voltage VIN is smaller than the reference voltage VREF. When offset is not exit in the comparator 110, the reference voltage VREF should be a boundary. where the resolution of a digital signal DIG<0:N−1>, acquired by analog-to-digital converting the input voltage VIN, changes. The value of the digital signal DIG<0:N-1> should be continuous at the boundary.
The resolution control unit 120 is configured to determine, in response to the comparison result of the comparator 110, the resolution of the analog-to-digital conversion by the analog-to-digital conversion unit 130. For example, in a case where the comparator 110 determines (in the case where the output of the comparator 110 has the logic low level) that the input voltage VIN is smaller than the reference voltage VREF, the resolution control unit 120 determines the resolution of the analog-to-digital conversion unit 130 as N bits. In a case where the comparator 110 determines (in the case where the output of the comparator 110 has the logic high level) that the input voltage VIN is than the reference voltage VREF, the resolution of the analog-to-digital conversion unit 130 as N−M bits.
The analog-to-digital conversion unit 130 is configured to analog-to-digital convert the input voltage VIN based on the resolution determined by the resolution control unit 120 and generate the digital signal DIG<0:N−1>.
The comparator may be configured using an operational amplifier or the like. In general, in a semiconductor circuit, such as an operational amplifier, an offset voltage exists. The offset voltage may be caused by an error in a design, a semiconductor fabrication process, an error in a package, or the external environment. In the case where a positive offset exists, the comparator 110 outputs a logic high level if the input voltage VIN is larger than the sum of the reference voltage VREF and an offset voltage. Otherwise, the comparator 110 outputs a logic low level. In the case where a negative offset exists, the comparator 110 outputs a logic high level if the input voltage VIN is larger than the difference between the reference voltage VREF and an offset voltage. Otherwise, the comparator 110 outputs a logic low level. FIG. 2 is a graph explaining a non-linear error occurring due to an offset that exists in the comparator 110. FIG. 2 shows the digital signal DIG<0:N−1> according to the magnitude of the input voltage VIN.
L1 shows the digital signal DIG<0:N−1> based on a magnitude of the input voltage VIN, in a case where an offset does not exist in the comparator 110. L2 shows the digital signal DIG<0:N−1> based a magnitude of the input voltage VIN, in a case where a positive offset exists in the comparator 110. L3 shows the digital signal DIG<0:N−1> based on a magnitude of the input voltage VIN, in the case where a negative offset exists in the comparator 110.
In an ideal case, the slope (proportional to a resolution) of a graph should be changed at a point where the input voltage VIN becomes the same as the reference voltage VREF, as in L1, and the graph should be continuous at the point where the input voltage VIN is the reference voltage VREF. However, in the case where a positive offset exists in the comparator 110, the slope of a graph is changed at a point where the input voltage VIN is the same as the sum of the reference voltage VREF and an offset voltage VOFF, as in L2, and the graph is not continuous at that point and a non-linear error occurs. Also, in the case where a negative offset exists in the comparator 110, the slope of a graph is changed at a point where the input voltage VIN is the same as the difference between the reference voltage VREF and the offset voltage VOFF, as in L3, and the graph is not continuous at that point and a non-linear error occurs. Such non-linear errors exert negative influences on the precision of an analog-to-digital convertor.